Due to the advancement of semiconductor integrated circuit manufacturing technology, not only is the quantity of the memory cells contained in a non-volatile memory ever-increasing, but the dimensions of constituent elements are also becoming smaller because of increasingly high integration.
To ensure the stability of memory cells in operation and bring memory performance into full play, it is necessary that the memory cells in a non-volatile memory have to be appropriately insulated or isolated from each other, regardless of the extent of the scaling-down of the dimensions of the constituent elements.
Referring to FIG. 1, there is shown a top view of a conventional non-volatile memory array. FIG. 1 shows the non-volatile memory array in part, wherein the memory array comprises a plurality of gate structures 102 functioning as SONOS memory cells. The gate structures 102 are connected by the controlling gates 102d to form word lines arranged transversely. Each said gate structure 102 is adjacent to a drain region 106 and a source region 104 which are parallel to the word lines. Referring to FIG. 1, a source line contact window 122 is disposed on the source region 104 between two neighboring word lines. The source line contact windows 122 are each filled with barrier pins and connected together above by means of a source line (not shown), such that the source regions 104 separated by isolation structures 110 are electrically connected to form source lines. A bit line contact window 124 is disposed on the drain region 106. The bit line contact windows 124 are each filled with barrier pins and connected together above by means of a bit line (not shown), such that the drain regions 106 separated by the isolation structures 110 are connected above to form bit lines.
However, due to the presence of the contact windows 122, 124 and the barrier pins, dimension scaling down is achieved at the cost of a difficult process and deterioration of product yield.